1. Field of the Invention
The invention relates in general to an electrostatic discharge protection circuit and a fabrication method thereof, and more particularly, to an electrostatic discharge protection circuit of a non-gated diode and a fabrication method thereof that uses the silicon-on-insulation (SOI) fabrication process.
2. Description of the Related Art
Silicon-on-insulator technology is a prime contender for low voltage, and high-speed applications because of its advantages over bulk-Si technology in high isolation, latch-up immunity, and smaller junction capacitance. However, electrostatic discharge (ESD) is a major concern for SOI technology.
The protection level provided by an ESD protection circuit is determined by the amount of current that it can sink while clamping the voltage to a small value. The device failure is initiated by thermal runaway and followed by catastrophic damage during an ESD pulse. In SOI devices, the presence of the buried oxide layer having a thermal conductivity 1/100th of Si causes increased device heating, which in turn accelerates thermal runaway under ESD stress condition.
FIG. 1 depicts a cross-sectional view of a gated-diode (called as Lubistor) in SOI published in the article of S. Voldman et al. “CMOS-on-SOI ESD protection networks,” in Proc. Of EOS/ESD Symp. 1996, pp. 291-301. As shown in FIG. 1, the SOI gated diode is formed on a SOI substrate which includes a substrate 10, a buried oxide layer 12 and a silicon layer. Shallow trench isolation (STI) structures 14 are formed in the silicon layer. A P+ region 20 and an N+ region 16 are formed in the silicon layer between the STI structures 14, while a N-type or P-type doped region 18 is formed in the silicon layer between the P+ region 20 and the N+ region 16. If the N-type doped region 18 is selected, the P+ region 20 and the N− doped region 18 construct a SOI diode. In contrast, if the P-type doped region 18 is formed, the N+ region 16 and the P-type doped region 18 construct a SOI diode. A gate is further formed on the doped region 18. The gate includes a P+ region 24 and an N+ region, a spacer 26 and a gate oxide 28.
The P+ region 20 and the N+ region 16 are coupled to voltage V1 and V2 as the voltage application terminals for the SOI diode. Taking the SOI diode formed of the P+ region 20 and the N-type doped region 18 as an example, the SOI diode is forward biased if V1 is positive relative to V2. On the contrary, if V2 is positive relative to V1, the SOI diode is reverse biased.
If the heat generated by the ESD voltage at the junction between the P+ region 20 and the N-type doped region 18 is small, the SOI diode can withstand a higher ESD voltage. The heat generated at the PN junction is joule heating. When the maximum temperature of the SOI diode reaches its intrinsic temperature, Tintrinsic, second order breakdown occurs. Therefore, to obtain a better ESD protection, the power density and joule heating have to be reduced in the device structure.